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NTE2532 Integrated Circuit NMOS, 32K EPROM, 300ns
Description: The NTE2532 is a 32,768-bit, ultraviolet-light-erasable, electrically-programmable read-only memory in a 24-Lead DIP type package. This device is fabricated using N-channel silicon-gate technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be directly driven by Series 74 TTL circuits without the use of external pull- up reistors, and each output can drive one Series 74 circuit without external resistors. The data outputs are three-state for connecting mutiple devices to a common bus. Since the NTE2532 operates from a single +5V supply (in the read mode), it is ideal for use in microprocessor systems. One other (+25V) supply is needed for programming but all programming signals are TTL level, requiring a single 10ms pulse. For programming outside of the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Total programming time for all bits is 41 seconds. Features: D Organization: 4096 x 8 D Single +5V Power Supply D All Inputs/Outputs Fully TTL Compatible D Static Operation (No Clocks, No Refresh) D Max Acces/Min Cycle Time: 300ns D 8-Bit Output for Use in Microprocessor Based Systems D N-Channel Silicon-Gate Technology D 3-State Output Buffers D Low Power Dissipation: Active - 400mW Typical Standby - 100mW Standby D Guaranteed DC Noise Immunity with Standard TTL Loads D No Pull-Up Resistors Required Absolute Maximum Ratings: (TA = 0 to +70C, Note 1 unless otherwise specified) Supply Voltage (Note 2), VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Supply Voltage (Note 2), VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V All Input Voltages (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Output Voltage (Operating, with Respect to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +150C Note 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operation Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Note 2. Under absolute maximum ratings, voltage values are with respect to the most negative supply voltage, VS (substrate).
Recommended Operating Conditions:
Parameter Supply Voltage Symbol VCC VPP VSS High Level Input Voltage Low Level Input Voltage Read Cycle Time Operating Ambient Temperature VIH VIL tc(rd) TA Note 3 Note 4 Test Conditions Min 4.75 - - 2 -0.1 300 0 Typ 5.0 VCC 0 - - - - Max 5.25 - - VCC+1 +0.8 - 70 Unit V V V V V ns C
Note 3. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP is applied. Note 4. VPP can be connected to VCC directly (except in the programming mode). VCC supply current in this case would be ICC + IPP. During programming, VPP must be maintained at 25V (1V). Electrical Characteristics: (Over full range of recommended operating conditions)
Parameter High Level Output Voltage Low Level Output Voltage Input Current (Leakage) Output Current (Leakage) VPP Supply Current VPP Supply Current (During Program Pulse) VCC Supply Current (Standby) VCC Supply Current (Active) Symbol VOH VOL Il IO IPP1 IPP2 ICC1 ICC2 Test Conditions IOH = -400A IOL = 2.1mA VI = 0V to 5.25V VO = 0.4V to 5.25V VPP = 5.25V, PD/PGM = VIL PD/PGM = VIL PD/PGM = VIH PD/PGM = VIL Min 2.4 - - - - - - - Typ - - - - - - 20 80 Max - 0.45 10 10 12 30 -30 160 Unit V V A A mA mA mA mA
Capacitance: (Over recommended voltage and operating ambient temperature range, f = 1MHz, Note 5, Note 6)
Parameter Input Capacitance Output Capacitance Symbol Ci Co Test Conditions VI = 0V, f = 1MHz VO = 0V, f = 1MHz Min - - Typ 4 8 Max 6 12 Unit pF pF
Note 5. All typical values are at TA = +25C and nominal voltages. Note 6. Capacitance measurements are made on a sample basis only. Switching Characteristics: (Over full range of recommended operating conditions, Note 5, Note 8)
Parameter Access Time from Address Access Time from PD/PGM Output Data Valid after Address Change Output Disable Time from PD/PGM (Note 7) Symbol ta(A) ta(PR) tv(A) tdis Test Conditions CL = 100pF, 1 Series 74 TTL Load, tr 20ns, tf 20ns, Note 8, Note 9 Min - - 0 - Typ - - - - Max 300 300 - 100 Unit ns ns ns ns
Note Note Note Note
5. 7. 8. 9.
All typical values are at TA = +25C and nominal voltages. Value calculated from 0.5V delta to measured output level Timing measurement reference levels: inputs 0.8V and 2V, outputs 0.65V and 2.2V. Common test conditions apply for tdis except during programming. For ta(A) and tdis, PD/PGM = VIL.
Recommended Timing Requirement for Programming: (TA = +25C, Note 8, Note 10)
Parameter Pulse Duration, Program Pulse Rise Time, Program Pulse Fall Time, Program Pulse Address Setup Time Data Setup Time Setup Time for VPP Address Hold Time Data Hold Time Program Pulse Hold Time VPP Hold Time Symbol tw(PR) tr(PR) tf(PR) tsu(A) tsu(D) tsu(VPP) th(A) th(D) th(PR) th(VPP) Test Conditions Min 9 5 5 2 2 0 2 2 0 2 Typ - - - - - - - - - - Max - - - - - - - - - - Unit ms ns ns s s ns s s ns s
Note 8. Timing measurement reference levels: inputs 0.8V and 2V, outputs 0.65V and 2.2V. Note10. Typical values are at nominal voltages. Operation:
Function (Pins) Read PD/PGM (20) VPP (21) VCC (24) Q (9 to 11, 13 to 17) VIL +5V +5V Q Output Disable VIH +5V +5V High-Z Power Down VIH +5V +5V High-Z Mode Start Programming Inhibit Programming Pulsed VIH to VIL +25V +5V D VIH +25V +5V High-Z
Read/Out Disable When the outputs of two or more NTE2532s are connected on the same bus, the output of any particular device in the circuit can be read with no interference from the cpmpeting outputs of the other devices. The device whose output is to be read should have a low-level TTL signal applied to the PD/PGM pin. Output data is accessed at pins Q1 through Q8. Power Down Active power dissipation can be cut by over 70% by applying a high TTL signal to the PD/PGM pin. In this mode all outputs are in a high-impedance state. Erasure Before programming, the NTE2532 is erased by exposing the chip through the transparent lid to high- intensity ultraviolet light having a wavelength of 253.7nm (2537 angstroms). The recommended minimum exposure dose (UV intensity time exposure time) is fifteen watt-seconds per square centimeter. Thus, a typical 12 miliwatt per square centimeter filterless UV lamp will erase the device in a minimum of 21 minutes. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure, all bits are in the "1" state (assuming high-level output corresponds to logic "1"). It should be noted that normal ambient light contains the correct wavelenght for erasure. Therefore when using the NTE2532, th window should be covered with an opaque label. Start Programming After erasure (all bits in logic "1" state), logic "0's" are programmed into the desited locations. A "0" can be erasedonly by ultraviolet light. The programming mode is achieved when VPP is 25V. Data is presented in parallel (8 bits) on pins Q1 through Q8. Once addresses and data are stable, a 10-millisecond TTL low-level pulse should be applied the the PGM pin at each address location to be programmed. Maximum pulse width is 44 milliseconds. Locations can be programmed in any order. Several NTE2532s can be programmed simultaneously when the devices are connected in parallel.
Inhibit Programming When two or more devices are connected in parallel, data can be programmed into all devices or only chosen devices. Any NTE2532 not intended to be programmed should have a high level applied to PD/PGM. Programming Verification The NTE2532 program verification is simply the read operation, which can be performed as soon as VPP returns to +5V ending the program cycle.
Pin Connection Diagram
A7 A6 A5 A4 A3 A2 A1 A0 Q1 Q2 Q3 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC A8 A9 VPP PD/PGM A10 A11 Q8 Q7 Q6 Q5 Q4
1.290 (32.76) Max
.600 (15.24) Max Glass
24
13 .520 (13.2)
1
12 .280 (7.11) Dia UV Window Glass Sealant
.160 (4.06) Max .200 (5.08) Max
.100 (2.54)
.125 (3.17)
.670 (17.02)

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